The present invention relates to semiconductor devices, such as flash memory devices, more particularly to a method and system for reducing removal of the antireflective-coating by condensing the ARC layer.
A conventional semiconductor device, such as a conventional embedded flash memory, includes a large number of memory cells in a memory region. The memory cells are typically floating gate devices, such as floating gate transistors. The conventional embedded memory may also include logic devices in a second region, or core, of the conventional embedded memory. The logic and memory regions of the conventional embedded memory are typically processed separately.
FIG. 1 is a flow chart depicting a conventional method 10 for processing a portion of a conventional semiconductor device, such as a conventional embedded flash memory. A polysilicon layer is deposited across a semiconductor substrate, via step 12. The polysilicon layer is typically deposited on a thin insulating layer grown on the substrate. A conventional SiON antireflective coating (xe2x80x9cARCxe2x80x9d) layer of a desired thickness is then deposited, via step 14. The conventional ARC layer must be deposited in a very narrow range of the desired thickness in step 14. This is because the antireflective properties of the conventional ARC layer are highly dependent upon the thickness of the conventional ARC layer. Typically, the desired thickness of the conventional ARC layer is three hundred Angstroms plus or minus ten percent (thirty Angstroms).
A first photoresist layer is then patterned on the conventional ARC layer, via step 16. The first photoresist layer pattern is typically obtained by spinning a layer of photoresist onto the ARC layer and exposing portions of the photoresist layer to light through a mask layer to develop a pattern, or mask, in the photoresist layer. The first photoresist layer patterned in step 16 typically completely covers the logic region of the conventional imbedded memory. The first photoresist layer also includes a pattern over the memory region to define stacked gates in the memory region of the conventional imbedded memory.
Once the first photoresist pattern has been defined, the stacked gates of the memory region are etched, via step 18. The first resist layer is then removed and residues cleaned using a wet etch, via step 20. A second photoresist pattern is then defined, via step 22. Step 22 typically includes spinning a second layer of photoresist onto the conventional embedded memory and developing the pattern of the second photoresist structure using conventional photolithography. Masking in the second photoresist layer defines gates in the logic region of the conventional imbedded memory, while the second photoresist layer also covers the memory region to ensure that processing of the logic region does not affect the memory region. The gates in the logic region are then etched, via step 24. The second photoresist layer may then be stripped and residues cleaned, via step 26. Processing of the conventional imbedded memory is then completed, via step 28.
Although the conventional method 10 can be used, one of ordinary skill in the art will readily understand that the conventional method 10 results variations in the critical dimension of structures fabricated in the logic region of the conventional embedded memory. When photoresist is spun onto the conventional embedded memory in steps 16 or 22, the photoresist will vary in thickness. This is particularly true when the topology of the layers under the photoresist is not flat.
Variations in the photoresist layer thickness cause variations in the critical dimension of structures desired to be formed, otherwise known as the swing curve effect. FIG. 2 is a graph 30 depicting the swing curve effect, variations in critical dimension versus photoresist thickness. The plot 31 indicates the desired size, or desired critical dimension, of a particular feature. The desired size is set by the design of the conventional embedded memory and thus is independent of resist thickness. The plot 32 depicts the variation in critical dimension versus photoresist thickness when a conventional ARC layer of the appropriate thickness is used. Because the conventional ARC layer of the appropriate thickness is used, reflections from the layer(s) underlying the photoresist layer are reduced. Thus, the structures formed using the photoresist layer have a critical dimension that is close to the desired critical dimension.
Curve 34 depicts the variation in the critical dimension for the structure of the desired size when no conventional ARC layer or a conventional ARC layer of an incorrect thickness is used. The antireflective properties of the ARC layer are highly dependent on thickness of the ARC layer. When a resist pattern is formed without the ARC layer, light used in conventional photolithography may reflect off of the layer(s) and structures under the photoresist layer. The reflected light causes variations in critical dimensions of structures etched in the polysilicon layer and causes a phenomenon called reflective notching, a narrowing of the polysilicon lines as a result of reflections from the underlayer. Thus, the critical dimensions of structures fabricated with no conventional ARC layer or a conventional ARC layer without the desired thickness vary more strongly with photoresist thickness. This variation is shown in curve 34.
FIG. 3A depicts a portion of a conventional embedded memory 40 after step 16, patterning the first resist layer, is performed. The conventional embedded memory 40 includes a logic region 44 and a memory region 42. A polysilicon layer 51 is provided on substrate 50. Note that an insulating layer (not shown) typically separates the polysilicon layer 51 from the substrate 50. In addition, underlying structures 47 and 49 are shown. Structures 47 and 49 were obtained prior to deposition of the polysilicon layer 51. A conventional ARC layer 52 having the desired thickness for reducing reflections is provided on the polysilicon layer 51. The thickness of the conventional ARC layer 52 is typically three hundred Angstroms plus or minus approximately ten percent. The first photoresist structure 53 covers the logic region 44, but defines the pattern for stacked gates in the memory region 42. Note that the first photoresist structure 53 varies in thickness.
FIG. 3B depicts a portion of a conventional embedded memory 40 after step 18, etching gates in the memory region 42, of the method 10 shown in FIG. I is performed. Referring to FIG. 3B, stacked gates 54, 56 and 58 have been formed in the memory region 42 of the conventional embedded memory 40. The stacked gates 54, 56 and 58 are covered by remaining portions 55, 57 and 59, respectively, of the ARC layer 52. Portions of the first photoresist layer 53 still covers the stacked gates 54, 56 and 58 as well as the polysilicon layer 51 and the conventional ARC layer 52 in the logic region 44. Because the conventional ARC layer 52 has the desired thickness, the critical dimensions of gates 54, 56 and 58 are quite close to what is desired. In other words, variations in the critical dimension of the gates 54, 56 and 58 may follow the curve 32 depicted in FIG. 2.
FIG. 3C depicts a portion of a conventional embedded memory 40 after step 20, stripping the first photoresist structure 53, of the method 10 shown in FIG. 1 is performed. Referring to FIG. 3C, a portion of the conventional ARC layer 52 has been removed during the strip of the photoresist structure 53. Thus, the conventional ARC layer 52 is thinner than in FIG. 3B. Typically, twenty to fifty Angstroms are removed during the wet resist strip after the etch performed in step 20. After the etch, the thickness of the conventional ARC layer 52 is twenty to fifty Angstroms thinner than the optimal thickness. Consequently, removal of a portion of the conventional ARC layer 52 during the resist strip is likely to significantly reduce the ability of the conventional ARC layer 52 to decrease reflections. Thus, the gates formed in step 24 in the logic region 44 will have critical dimensions which vary greatly. In other words, the critical dimensions of structures, such as gates, in the logic region will follow the curve 44 shown in FIG. 2. These large variations are undesirable. In order to reduce these variations in the logic region 44, the ARC layer 52 and photoresist structure 53 would be removed. The ARC layer 52 would then be replaced with another ARC layer (not shown) that is deposited at the desired thickness.
Accordingly, what is needed is a system and method for providing the conventional semiconductor device, such as an imbedded memory, in which the ARC layer need not be removed and redeposited. The present invention addresses such a need.
The present invention provides a method and system for providing a semiconductor device. The method and system comprise depositing an antireflective coating (ARC) layer having antireflective properties. The method and system also comprise depositing a capping layer on the ARC layer. The capping layer reduces a susceptibility of the ARC layer to removal while allowing the ARC layer to substantially retain the antireflective properties.
According to the system and method disclosed herein, the present invention reduces the removal of the ARC layer during a photoresist strip by providing the capping layer on the ARC layer. Consequently, the ARC properties of the ARC layer are preserved, allowing a reduction in the swing curve effect and reflective notching.